Your browser cookies must be enabled in order to apply for this job. Please contact support@jobscore.com if you need further instruction on how to do that.

Principal RFIC Designer

Engineering | Sunnyvale, CA | Full Time

Job Description

About Us:

Kumu Networks is revolutionizing the way wireless and wired systems are built using self-interference-cancellation to enable an innovative full-duplex design that its co-founders developed at Stanford University. In particular wireless full duplex allows a radio to transmit and receive signals at the same time using the same frequency channel. Kumu's patent pending technology changes the basic assumptions on which current wireless radios are built, allowing for improved performance and reduced complexity across a variety of wireless devices and markets. Come help us change the future of wireless!

 

Description:

The Principal RFIC Design Engineer will be a key contributor to the evolution of Kumu Networks full-duplex technology. He/she will work with Kumu’s core technology team to drive the miniaturization of self-interference cancellation into integrated circuits. The ideal candidate will have excellent fundamentals and understand the pros and cons of different RF and analog implementations of a desired function, as well as possess the creativity to use standard components in nontraditional and very innovative ways. The candidate will also have a deep understanding of different IC technologies (standard CMOS and RFSOI,) and the design flow from concept all the way through to release for production. The candidate will be the focus point and reference person where tough challenges of design would be solved by him/her.

 

Responsibilities:

  • Lead the design of on-chip blocks such as wide dynamic range LNA, down conversion and up conversion modulators/demodulators (mixers), Variable gain amplifiers, LO chains, Baluns, baseband filters, RF switches, attenuators, summing amplifiers and biasing circuits.
  • Generate new topologies and architectures to achieve very challenging system requirements
  • Create floorplanning of entire layout and assist in on-chip layout
  • Evaluate the designed on-chip circuits in the lab either in hand- or automated measurements
  • Discuss block and system performance with System Engineers
  • Prepare and participate in design, spec and layout reviews

 

 

Requirements:

  • Bachelor with 10+,  Master with 8+ or Ph.D. with 6+ experience (preferred) degree in Electrical Engineering.
  • Hands-on experience in the design of complex chips (e.g. transceivers, wireless sensors, PLLs or convertors)
  • Ability to work and learn in a team
  • Familiar with Cadence Virtuoso design software and Assura as well as ADS by Agilent.
  • Familiar with standard CMOS, CMOS on SOI and BiCMOS technologyFamiliar with lab test setups using signal analyzers, VNAs, signal generators, digital oscilloscopes, power meters, etc.

 

Bonus Points:

  • Experience with integrated passives design (IPD)
  • Familiarity with MatLab is a plus
  • Knowledge of Python or C (for test and analysis scripting)
  • Experience with PCB level simulations and layout tools
  • Having worked with field solvers or inductor generators is a bonus

 

 

Perks:

  • Lunch provided daily
  • Sunny, open, collaborative workspace
  • Opportunity to work with great people on fundamentally new technologies

 

Keywords; 

RF, Analog, CMOS, SOC, LNA, Mixer, transceiver, and SOI.