Lead/Principal Digital Design Engineer
Engineering | Sunnyvale, CA | Full Time
960 Hamlin Court Sunnyvale, California 94089
LEAD/PRINCIPAL DIGITAL DESIGN ENGINEER
Kumu Networks is revolutionizing the way wireless systems are built using innovative self-interference cancellation technology that enables a host of new wireless applications. Wireless full-duplex allows a radio to transmit and receive signals at the same time using a single frequency channel. Adjacent-channel cancellation systems do away with the need for expensive filters, enabling multiple devices to share spectrum in more intelligent ways. Kumu's patented technology changes the basic assumptions on which current wireless radios are built, allowing for improved performance and reduced complexity across a variety of wireless devices and markets. Come help us change the future of wireless!
The Digital Design Engineer is responsible for the end-to-end, top-level design of the digital subsystem in the world’s first integrated cancellation SoC. They will work with the RFIC design, systems, and software engineering teams to architect the correct digital subsystem, including a processor, memory controllers, digital/mixed-signal interfaces, and custom DSP acceleration blocks. The engineer will use a combination of design techniques, ranging from evaluating/integrating standard IPs, to specifying custom blocks for development by 3rd parties, to designing some critical blocks on their own. On the back-end, the engineer will work with third parties to make sure that simulation, timing, routing, DFT / DFM and functionality requirements are met. The engineer will own the overall functionality and first-time right correctness of the design. The ideal candidate will work well with the system architects, contribute to the overall design of the system, and collaborate with mixed-signal/RF as well as embedded software engineers.
• Work with systems, software, and RFIC engineers to specify, design, implement, verify, and test a complex embedded, fully customized SoC
• Participate in selection/requirements analysis for various digital subsystems
• Manage external & internal resources to ensure that purchased, designed, or standard modules meet specifications and interface correctly with the rest of the system
• Implement custom digital blocks in Verilog
• Develop and maintain an automated test environment for digital subsystem verification, both with initial RTL and with pre- and post-timing netlists
• Create and maintain FPGA image of the SoC for system emulation testing
• Manage external contractors / third party vendors for running backend flows for synthesis, place and route, design for test, BIST insertion etc.
• 15+ years of experience designing and architecting digital SoCs, with designs proven in silicon
• Fluent in Verilog and able to rapidly design, test, and verify systems
• Fluent in scripting languages useful for place and route as well as test automation
• Comfortable with Cadence / Synopsys tools for digital design, including - but not limited to RTL simulation, design verification, synthesis and equivalence checking, place and route, scan and BIST insertion etc.
• Comfortable with the entire design flow for digital and mixed signal chips including specification, RTL, verification, back-end, tape-out and validation
• Knowledge of standard methodologies with respect to implementation of digital logic Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation
• Understanding of Design Verification and the ability to write self-checking test suites
• Experience in hands-on lab evaluation
• Working with Physical Design Team on STA, physical, power and logical issues
• Able to give accurate estimates of deadlines and milestones as well as meet them
• Worked on modem and or transceiver products, including calibration routines
• Experience with DSP fixed-point digital design
• Lunch available daily
• Sunny, open, ergonomic and collaborative workspace
• Opportunity to work with great people on challenging technology